Apple is expected to use TSMC's new 2nm process and SoIC-X (System on Integrated Chip) advanced packaging technology in the second half of 2025, according to new reports. AMD was the first to adopt ...

The problem is well-known: programming and debug headers consume valuable board space and the connectors cost money. Especially troublesome are the ubiquitous 100-mil pin headers, not because they’re ...

TL;DR: Apple is collaborating with TSMC to adopt advanced WMCM and SoIC packaging technologies for its next-generation A20 and server chips in 2026. These innovations enable ultra-dense chip stacking, ...

The AI surge requires TSMC to swiftly expand its production capacity for chip-on-wafer-on-substrate (CoWoS) packaging. Simultaneously, the foundry's production capacity for 3D-stacked ...

HSINCHU, July 15, 2025 /PRNewswire/ -- InPsytech, a leading provider of high-speed semiconductor IP solutions and a member of the Egis Group, announced that it has successfully taped out its advanced ...

InPsytech, a leading company under the Egis Technology Group specializing in high-speed semiconductor IP solutions, has completed its advanced design for TSMC's Face-to-Face (F2F) SoIC technology, ...

[Pyra] was looking for a way to reprogram some ATtiny13 microcontrollers in a SOIC package. He’s re-engineering some consumer electronics so adding an ISP header to the design isn’t an option. He had ...

At the Chiayi AP7 site, the report notes that equipment installation—originally scheduled for the end of 2025—has been moved forward to August 2025. The priority at this site is to ramp up production ...

Supporting 24-, 28-, and 32-pin SOC and SOJ devices, a line of SOIC- and SOJ-to-DIP adapters eliminates the need for changing PCB layouts. The devices have centerline spacing of 10.16 and 15.24 mm, ...

Allegro MicroSystems had introduced 1MHz bandwidth current sensors that can measure hundreds of amps – the first fruit of its acquisition of Crocus Technologies. The technology is tunneling ...

IXYS Corporation announced its new 60 V, dual and normally open solid-state relay with the highest current rating in a SOIC package. It provides 400 V of input-to-output isolation; and comprises two ...